VHDL数字电路设计教程第六章习题答案_vhdl数字电路设计教程
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P6.1 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity chp6_1 is port(clk:in std_logic;
d_out:out std_logic_vector(5 downto 0));end;architecture bhv of chp6_1 is
signal count: std_logic_vector(5 downto 0);
signal temp: std_logic_vector(5 downto 0);begin
proce(clk)
begin
if clk'event and clk='1' then
count
if count=“100000” then count
end if;
end if;
end proce;proce(clk)
begin
if clk'event and clk='0' then
temp
if temp=“0111111” then temp
end if;end if;end proce;
d_out
solution1 library ieee;use ieee.std_logic_1164.all;entity chp6_3 is port(x:in std_Logic_vector(7 downto 1);
y:out std_logic_vector(2 downto 0));end;architecture bhv of chp6_3 is begin
proce(x)
begin
if x(7)='1' then y
elsif x(6)='1' then y
elsif x(5)='1' then y
elsif x(4)='1' then y
elsif x(3)='1' then y
elsif x(2)='1' then y
elsif x(1)='1' then y
else y
end if;
end proce;end;solution2 library ieee;use ieee.std_logic_1164.all;entity chp6_3_2 is generic(n:integer:=3);port(x:in std_logic_vector(2**n-1 downto 0);
y:out integer range 0 to 2**n-1);end;architecture bhv of chp6_3_2 is begin
proce(x)
variable temp:integer range 0 to 2**n-1;
begin
for i in x'range loop
if x(i)='1' then
temp:=i;
exit;
end if;
end loop;
y
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity chp6_4 is generic(n:integer:=8);port(clk:in std_logic;
clk_out:out std_logic);end;architecture bhv of chp6_4 is signal rst:std_logic;signal temp:std_logic_vector(2 downto 0);begin proce(clk,rst)begin
if rst='1' then
temp
elsif clk'event and clk='1' then
temp
end if;end proce;
rst
'0';
clk_out
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity chp6_5 is generic(n:integer:=7);port(clk:in std_logic;
clk_out:out std_logic);end;architecture bhv of chp6_5 is signal temp:std_logic_vector(2 downto 0);signal cout:std_logic;begin proce(clk)begin
if clk'event and clk='1' then
temp
if temp=“110” then temp
end if;
end if;
end proce;
cout
'0';
clk_out
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity chp6_6 is
port(clk,start,stop,reset:in std_logic;
dig1,dig2,dig3:out std_logic_vector(3 downto 0));end;architecture bhv of chp6_6 is signal sec1:integer range 0 to 10;signal sec2:integer range 0 to 6;signal min:integer range 0 to 10;begin
proce(clk,start, stop,reset)
variable count1:integer range 0 to 10;
variable count2:integer range 0 to 6;
variable count3:integer range 0 to 10;
begin
if reset='1' then
count1:=0;
count2:=0;
count3:=0;
elsif clk'event and clk='1' then
if start='1' and stop='0' then
count1:=count1+1;
if count1=10 then
count1:=0;count2:=count2+1;
if count2=6 then
count2:=0;count3:=count3+1;
if count3=10 then
count3:=0;
end if;
end if;
end if;
end if;
end if;
sec1
sec2
min
dig1
dig2
dig3
output:out std_logic);end;architecture bhv of chp6_8 is begin
proce(input)
variable temp:std_logic_vector(n-1 downto 0);
begin
temp(0):=input(0);
for i in 1 to n-1 loop
temp(i):=input(i)xor temp(i-1);
end loop;
output
P6.9 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity chp6_9 is
generic(n:integer:=4);
port(input:std_logic_vector(n-1 downto 0);
output:out integer range 0 to n);end;architecture bhv of chp6_9 is begin proce(input)
variable temp:integer range 0 to n;begin
temp:=0;
for i in 0 to n-1 loop
if input(i)='1' then
temp:=temp+1;
end if;
end loop;
output
dout:out std_logic_vector(n-1 downto 0));end;architecture bhv of chp6_10 is begin proce(din)
begin
for i in 0 to n-1 loop
if din=i then dout'1', others=>'0');
end if;
end loop;
end proce;end;P6.16
library ieee;use ieee.std_logic_1164.all;entity chp6_16 is generic(n:integer:=8);port(a,b:in std_logic_vector(n-1 downto 0);
cin:in std_logic;
s:out std_logic_vector(n-1 downto 0);
cout:out std_logic);end;architecture bhv of chp6_16 is signal carry:std_logic_vector(n downto 0);begin proce(a,b,cin,carry)begin
carry(0)
for i in 0 to n-1 loop
s(i)
carry(i+1)
end loop;
cout
end proce;end;说明：本次答案均为课上讨论过的，P6.11-P6.15均可参考第五章答案，可以利用对应语句将其放入进程中。
