(成都大学)EDA课程设计题目及解决方案(抢答器)_eda课程设计抢答器
(成都大学)EDA课程设计题目及解决方案(抢答器)由刀豆文库小编整理，希望给你工作、学习、生活带来方便，猜你可能喜欢“eda课程设计抢答器”。
EDA课程设计
设计题目：
智力竞赛抢答器 一．电路功能：
可满足8个组，同时参加竞赛。抢答器复位后，数码显示为0，在竞赛主持人出完题并示意抢答开始后，每个组都可以通过各自的按钮开关发出抢答信号，抢答器一旦接收到某组最先发出的信号后，立即让数码管显出该组的组号，同时发出音响提示，且对后来组发出的抢答信号一律不与理睬。主持人用复位钮复位抢答器，数码显示归0，提示音停止，在抢答组回答完问题后，重复前述过程，可进行下一题抢答。
二．原理框图（见附图）
三．设计要求
用VHDL语言描述抢答器逻辑功能，经编译后仿真，仿真波形正确后，加上段码译码器编译通过后方可在实验箱上下载，做真实电路验证。四.撰写设计报告
给出设计方案框图，包括模块的划分，信息的传递关系；给出各模块的VHDL程序；给出每个模块的仿真波形图，并附以文字说明；写出设计的心得体会和收获。
一．结构描述法1（先锁存后编码）
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY scq_8 IS
PORT(g: IN STD_LOGIC_VECTOR(8 DOWNTO 1);
rst, en: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(8 DOWNTO 1));END scq_8;ARCHITECTURE one OF scq_8 IS BEGIN
PROCESS(rst, en)
BEGIN
IF rst='0' THEN
q
ELSIF
en ='1' THEN
q
END IF;
END PROCESS;
END one;
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY bm8_4 IS
PORT(d: IN STD_LOGIC_VECTOR(8 DOWNTO 1);
sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END bm8_4;ARCHITECTURE one OF bm8_4 IS BEGIN
PROCESS(d)
BEGIN
CASE d IS
WHEN “11111110” => sum
WHEN “11111101” => sum
WHEN “11111011” => sum
WHEN “11110111” => sum
WHEN “11101111” => sum
WHEN “11011111” => sum
WHEN “10111111” => sum
WHEN “01111111” => sum
WHEN OTHERS => sum
END CASE;
END PROCESS;
END one;
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECL7S IS
PORT(A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END;ARCHITECTURE one OF DECL7S IS BEGIN
PROCESS(A)
BEGIN
CASE A IS
WHEN “0000” => LED7S
WHEN “0001” => LED7S
WHEN “0010” => LED7S
WHEN “0011” => LED7S
WHEN “0100” => LED7S
WHEN “0101” => LED7S
WHEN “0110” => LED7S
WHEN “0111” => LED7S
WHEN “1000” => LED7S
WHEN “1001” => LED7S
WHEN “1010” => LED7S
WHEN “1011” => LED7S
WHEN “1100” => LED7S
WHEN “1101” => LED7S
WHEN “1110” => LED7S
WHEN “1111” => LED7S
WHEN OTHERS => NULL;
END CASE;
END PROCESS;END;
四．状态机描述法
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY qdq8_1 IS
PORT(rst,clk: STD_LOGIC;
g: IN STD_LOGIC_VECTOR(8 DOWNTO 1);
q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sq: OUT STD_LOGIC);END qdq8_1;ARCHITECTURE one OF qdq8_1 IS
TYPE s IS(s0,s1);
SIGNAL crt_s: s;
SIGNAL sum: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN
PROCESS(rst,clk,g)
BEGIN
IF rst='0' THEN crt_s
ELSIF clk'event AND clk='1' THEN
CASE crt_s IS
WHEN s0 => q
CASE g IS
WHEN “11111110” => sum
WHEN “11111101” => sum
WHEN “11111011” => sum
WHEN “11110111” => sum
WHEN “11101111” => sum
WHEN “11011111” => sum
WHEN “10111111” => sum
WHEN “01111111” => sum
WHEN OTHERS => crt_s
END CASE;
WHEN s1 => q
END CASE;
END IF;
END PROCESS;END one;
