EDA课程设计——基于DDS的正弦信号发生器设计_dds发生器的课程设计
EDA课程设计——基于DDS的正弦信号发生器设计由刀豆文库小编整理，希望给你工作、学习、生活带来方便，猜你可能喜欢“dds发生器的课程设计”。
顶层文件 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DDS IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));END ENTITY DDS;ARCHITECTURE BEHAVE OF DDS IS
COMPONENT SUM99 IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
CLK:IN STD_LOGIC;
OUT1:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT SUM99;
COMPONENT REG1 IS
PORT(D:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT REG1;
COMPONENT ROM IS
PORT(CLK:IN STD_LOGIC;
ADDR:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
OUTP:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END COMPONENT ROM;
COMPONENT REG2 IS
PORT(D:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END COMPONENT REG2;
SIGNAL S1:STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL S2:STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL S3:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
U0:SUM99
PORT MAP(K=>K,EN=>EN,RESET=>RESET,CLK=>CLK,OUT1=>S1);
U1:REG1 PORT MAP(D=>S1,CLK=>CLK,Q=>S1);
U2:ROM PORT MAP(ADDR=>S2,CLK=>CLK,OUTP=>S3);
U3:REG2 PORT MAP(D=>S3,CLK=>CLK,Q=>Q);END ARCHITECTURE BEHAVE;
正弦查找表 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ROM IS PORT(ADDR:IN STD_LOGIC_VECTOR(6 DOWNTO 0);CLK:IN STD_LOGIC;OUTP:OUT SIGNED(7 DOWNTO 0));END ENTITY ROM;ARCHITECTURE ART OF ROM IS BEGIN PROCESS(CLK)IS BEGIN IF(CLK'EVENT AND CLK='1')THEN CASE ADDR IS WHEN “0000000”=>OUTPOUTPOUTPOUTPOUTP
WHEN “0000101”=>OUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTP
WHEN “0010010”=>OUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTP
WHEN “0011010”=>OUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTP
WHEN “0110000”=>OUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTP
WHEN “1000110”=>OUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTP
WHEN “1011100”=>OUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTP
WHEN “1110010”=>OUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTPOUTP
END CASE;
END IF;END PROCESS;END ARCHITECTURE ART;
DAC 0832的VHDL程序 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY DAC0832 IS PORT(CLK:IN STD_LOGIC;
RST:IN STD_LOGIC;
ILE:OUT STD_LOGIC;
CONT:OUT STD_LOGIC;DATA_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END ENTITY;ARCHITECTURE BEHAVE OF DAC0832 IS SIGNAL Q:INTEGER RANGE 0 TO 63;SIGNAL DATA:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN
PROCESS(CLK)
BEGIN
IF RST='1'THEN Q
IF DATA=“11111111”THEN DATA
ELSE DATA
END IF;
ELSE Q
END IF;
END PROCESS;ILE
频率控制字 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY REG0 IS
PORT(CLK:IN STD_LOGIC;
LOCK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));END ENTITY REG0;ARCHITECTURE ART OF REG0 IS BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF LOCK='1'THEN
Q
END IF;
END IF;
END PROCESS;END ARCHITECTURE ART;
相位寄存器 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG1 IS
PORT(D:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));END ENTITY REG1;ARCHITECTURE BEHAVE OF REG1 IS BEGIN
PROCESS(CLK)IS
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
Q
END IF;
END PROCESS;END ARCHITECTURE BEHAVE;
输出数据寄存器 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG2 IS PORT(D:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));END ENTITY REG2;ARCHITECTURE BEHAVE OF REG2 IS BEGIN
PROCESS(CLK)IS
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
Q
END IF;
END PROCESS;END ARCHITECTURE BEHAVE;
相位累加器 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SUM99 IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC:
OUT1:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));END ENTITY SUM99;ARCHITECTURE BEHAVE OF SUM99 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(9 DOWNTO 0);BEGIN
PROCESS(CLK,EN,RESET)IS
BEGIN
IF RESET='1'THEN
TEMP
ELSE
IF CLK'EVENT AND CLK='1'THEN
IF EN='1'THEN
TEMP
END IF;
END IF;
END IF;
OUT1
END PROCESS;END ARCHITECTURE BEHAVE;
图1.顶层电路原理图
图2.dds波形仿真图
图3.rom波形仿真图
图4.相位寄存器reg1仿真波形图
图5.寄存器reg2的波形仿真
图6.相位累加器仿真波形图
图7.优化过程及对比波形（A——H）
图A
图B
图C
图D
图E 23
图F
图G
图H
