2hz的4分频 产生控制信号_脉冲分频信号产生器

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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TESTFP IS

PORT(CLKK: IN STD_LOGIC;

CNT_EN,CNT_RST,LOAD:OUT STD_LOGIC);END;

ARCHITECTURE ONE OF TESTFP IS

SIGNAL DIV2CLK:STD_LOGIC;

SIGNAL DIV4CLK:STD_LOGIC;

BEGIN

N1:PROCESS(CLKK)

BEGIN

IF CLKK'EVENT AND CLKK='1'

THEN DIV2CLK

END IF;

END PROCESS N1;

N2:PROCESS(DIV2CLK)

BEGIN

IF DIV2CLK'EVENT AND DIV2CLK='1'

THEN DIV4CLK

END IF;

END PROCESS N2;

N3:PROCESS(CLKK,DIV4CLK)

BEGIN

IF CLKK='0' AND DIV2CLK='0' AND DIV4CLK='0'THEN CNT_RST

ELSE CNT_RST

END IF;

END PROCESS N3;

LOAD

CNT_EN

END;